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| data bulletin MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. sub-audio signaling processor features non-predictive ctcss tone decoder dcs sub-audio signal demodulator ctcss /nrz encoder with tx level adjustment and lowpass filter output stage with optional nrz pre-emphasis selectable sub-audio bandstop filter notone (ctcss rx) period timer low power operation member of dbs800 family (c-bus compatible) rx sub-audio in rx lpf rx amp amp in amp out rx sub-audio out comparator amp comparator nrz rx data and baud rate extractor + + _ _ digital noise filter frequency assesment notone timer frequency measurement c-bus interface and control logic tx level adjust notone command data reply data interrupt serial clock wake address select tx sub-audio out tx sub-audio lpf audio out audio bypass clock generator audio in xtal/ clock xtal in out v dd v ss v bias nrz tx data nrz rx baud rate nrz rx data ctcss sub- audio frequency chip select raw nrz data rx tx sub-audio bandstop audio signal path variable bandwidth 180hz/260hz data buffer and shift register the MX805A is a sub-audio frequency signaling processor that provides outband audio and digital signaling capability for lmr systems. designed for the transmission and non-predictive reception of continuous tone controlled squelch (ctcss) tones and other non-standard frequencies, the MX805A also handles non- return-to zero (nrz) data reception and transmission to provide digitally coded squelch (dcs/dpl tm ) and ltr tm signaling. setting the MX805A functions and modes is accomplished by data loaded from the microcontroller to the controlling registers within the device. reply data and interrupt protocol keep the microcontroller up to date on the operational status of the circuitry. ctcss tone data for transmission is generated in the microcontroller, loaded to the ctcss tx frequency register, encoded and output as a tone via the tx sub- audio lpf. received non-predicted ctcss tone frequencies are measured and the resulting data, in the form of a 2-byte data word, is presented to the microcontroller for matching against a lookup table. noise filtering is provided to improve the signal quality prior to measurement. nrz coded data streams for transmission, when generated within a microcontroller, are loaded to the nrz tx data buffer and output, in 8-bit bytes, through the lowpass filter circuitry as subaudible signals. dcs turnoff tones can be added to the data signals by switching the MX805A to the ctcss transmit mode at the appropriate time. nrz coding is produced by the microcontroller and translated to subaudio signals by the MX805A. received nrz data is filtered, detected, and placed into the nrz data register, which is then available for transfer (one byte at a time) to the microcontroller for decoding by software. clock extraction circuitry is provided on-chip. tx ad rx baud rates are selectable. hardware and software are designed to allow consecutive addressing of two MX805A sub-audio signaling processors to achieve multi-mode duplex operation. powersaving may be controlled by software or by an input dedicated to the purpose. the MX805A may be used with a 5.0v power supply and is available in the following packages: 24-pin soic (MX805Adw), 24-pin plcc (MX805Alh), and 24-pin pdip (MX805Ap).
sub-audio signaling processor 2 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. contents section page 1 block diagram................................................................................................................ 4 2 signal list................................................................................................................... .... 5 3 external components.................................................................................................... 7 3.1 input configurations ........................................................................................................ ..... 8 3.1.1 using and external op-amp ................................................................................................. .... 8 4 general description....................................................................................................... 9 4.1 glossary .................................................................................................................... .......... 9 4.2 operating modes ............................................................................................................. .... 9 4.2.1 nrz encoding.............................................................................................................. ............. 9 4.2.2 ctcss encoding............................................................................................................ .......... 9 4.2.3 nrz decoding .............................................................................................................. .......... 10 4.2.4 ctcss decoding............................................................................................................ ........ 10 5 controlling protocol .................................................................................................... 10 5.1 MX805A internal registers................................................................................................ 10 5.1.1 control register (70 h /78 h ) .................................................................................................... 10 5.1.2 status register (71 h /79 h )...................................................................................................... 10 5.1.3 ctcss rx frequency register (72 h /7a h ) ............................................................................ 10 5.1.4 ctcss tx frequency/nrz tx or rx baud rate register (73 h /7b h ) ................................... 10 5.1.5 nrz rx data register (74 h /7c h ) .......................................................................................... 10 5.1.6 nrz tx data register (75 h /7d h ) .......................................................................................... 10 5.1.7 gain set register (76 h /7e h ).................................................................................................. 10 5.2 address/commands .......................................................................................................... 11 5.2.1 write to control register - a/c 70h (78h) followed by 1 byte of command data.................. 12 5.2.2 general reset............................................................................................................. ............ 12 5.2.3 read status register Ca/c 71 h (79 h ) followed by 1 byte of rely data................................. 13 5.2.4 read ctcss rx frequency register Ca/c 72 h (7a h ) followed by 2 bytes of reply data .. 13 5.2.5 write to ctcss tx frequency/nrz baud data rate register Ca/c 73 h (7b h ) followed by 2 bytes of command data. ................................................................................................ 15 5.2.6 read nrz rx data register C a/c 74 h (7c h ) followed by 1 byte reply data ..................... 17 5.2.7 write to nrz tx data register C a/c 75 h (7d h ) followed by 1 byte of command data. ..... 17 5.2.8 write to gain set register C a/c 76 h (7e h ) followed by 1 byte of command data .............. 17 sub-audio signaling processor 3 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 6 performance specifications........................................................................................ 18 6.1 electrical specifications................................................................................................... .. 18 6.1.1 absolute maximum limits................................................................................................... ........... 18 6.1.2 operating limits .......................................................................................................... .................. 18 6.1.3 operating characteristics ................................................................................................. ............. 19 6.1.4 timing.................................................................................................................... ........................ 22 6.2 packages.................................................................................................................... ....... 23 mxcom, inc. reserves the right to change specifications at any time without notice. sub-audio signaling processor 4 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 1 block diagram rx sub-audio in rx lpf rx amp amp in amp out rx sub-audio out comparator amp comparator nrz rx data and baud rate extractor + + _ _ digital noise filter frequency assesment notone timer frequency measurement c-bus interface and control logic tx level adjust notone command data reply data interrupt serial clock wake address select tx sub-audio out tx sub-audio lpf audio out audio bypass clock generator audio in xtal/ clock xtal in out v dd v ss v bias nrz tx data nrz rx baud rate nrz rx data ctcss sub- audio frequency chip select raw nrz data rx tx sub-audio bandstop audio signal path variable bandwidth 180hz/260hz data buffer and shift register figure 1: block diagram sub-audio signaling processor 5 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 2 signal list pin signal description 1 xtal the output from the on-chip clock oscillator inverter. external components are required at this input when a xtal input is used. see figure 2. 2 xtal/clock the input to the clock oscillator inverter. a xtal or externally derived clock should be connected here. 3 address select this input enables two MX805As to be used on the same c-bus to provide dull- duplex operation. see table 4 and table 5. 4 irq request interrupt . the output of this pin indicates an interrupt condition to the microcontroller by going to a logic 0. this wire-or-able output allows the connection of up to 8 peripherals to 1 interrupt port on the microcontroller. this pin has a low impedance pulldown to logic 0 when active, and a high impedance when inactive. the system irq line requires 1 pull-up resistor to v dd . the conditions that cause interrupts are indicated in the table 5 and table 7. 5 serial clock this is the c-bus serial clock input. this clock, produced by the microcontroller, is used for transfer timing of commands and data to and from the MX805A. see timing diagrams. 6 command data this is the c-bus serial data input from the microcontroller. data is loaded to this device in 8-bit bytes, msb (bit 7) first and lsb (bit 0) last, synchronized to the serial clock. see timing diagrams. 7 cs select chip . this is the c-bus data loading control function. this input is provided by the microcontroller. data transfer sequences are initiated, completed or aborted by the cs signal. see timing diagrams. 8 reply data this is the c-bus serial data output to the microcontroller. the transmission of reply data bytes is synchronized to the serial clock under the control of the cs input. this 3-state output is held at high impedance when not sending data to the microcontroller. see timing diagrams 9 tx sub-audio out this is the subaudio output (pure or nrz derived). signals are band limited. the tx output filter had a variable bandwidth (see table 9). this output is at v bias (a) when the nrz encoder is enabled but no data is being transmitted, (b) when the MX805A is placed in the powersave all condition. 10 audio in this is the input to the switched sub-audio bandstop (highpass) filter. it is internally biased, and should be ac coupled by capacitor c7. 11 audio out this is the output of the audio signal path (filter or bandpass). it is controlled by the control register. when disabled, the pin is held at v bias . 12 v ss negative supply (gnd) 13 rx amp in (-) this is the inverting input to the on-chip rx input amp. (see figure 2, figure 3, and figure 4). 14 rx amp in (+) this is the non-inverting input to the on-chip rx input amp. 15 rx amp out this is the output of the on-chip rx input op-amp. this circuit may be used, with external components, as a signal amplifier and anti-aliasing filter prior to the rx lowpass filter, or for other purposes. see figure 2 for component details. 16 rx sub-audio in this is the received sub-audio (ctcss/nrz) input. it is internally referenced to v bias . this signal to this pin should be ac coupled or biased. see figure 2. 17 rx sub-audio out this is the output of the rx lowpass filter. it may be coupled into the on-chip amplifier or comparator as required. 18 v bias the internal circuitry bias line, held at v dd /2. this pin must be decoupled to v ss by capacitor c8. see figure 2. 19 comparator in (-) this is the inverting input to the on-chip comparator amplifier. see figure 2, figure 3, and figure 4. 20 comparator in (+) this is the non-inverting input to the on-chip comparator amplifier. see figure 2, figure 3, and figure 4. sub-audio signaling processor 6 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. pin signal description 21 comparator out this is the output of the comparator amplifier. this node is also connected internally to the input of the /digital noise filter (see figure 1). when both decoders (ctcss or nrz) are powersaved, this output is at a logic 0. 22 notone timing external rc components connected to this pin form the timing mechanism of a notone period timer. the external network determines the charge rate of the timer to v bias . the expiration of the timer will cause an interrupt. this function is only used in the ctcss rx mode. see page 9. 23 wake this real time input can be used to reactivate the MX805A from the powersave all condition using an externally derived signal. the MX805A will be in powersave all condition when both this pin and bit 0 of the control register are set to a logic 1. recovery from powersave all is achieved by putting either the wake pin or the powersave all bit at logic 0. this allows MX805A activation by the microcontroller or an external signal, such as rssi or carrier detect. 24 v dd positive supply. a single 5.0v regulated supply is required. note: more information on external components and the dbs800 system integration of the MX805A are contained in the dbs800 system support documentation. guidance on the generation and manipulation of nrz and rx and tx data is given in the dbs800 application support documentation. c-bus: this is mx-coms proprietary standard for the transmission of commands and data between a microcontroller and dbs8000 microcircuits. it may be used with any microcontroller, and can, if desired, take advantage of the hardware and serial i/o functions embodied into many types of microcontroller. the c-bus data rate is determined by the microcontroller. table 1: signal list rx ctcss tone measurement completed ctcss notone timer expired 1 nrz rx data byte received new nrz data received before last byte read nrz tx buffer ready nrz data transmission complete table 2: interrupt conditions sub-audio signaling processor 7 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 3 external components 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 MX805Aj xtal irq cs xtal/clock address select serial clock command data reply data tx sub-audio out audio in audio out bias v v ss v dd dd wake notone comparator out comparator in (+) comparator in (-) v rx sub-audio out rx sub-audio in rx amp out rx amp in (+) rx amp in (-) see inset c7 r8 c5 c8 c4 + c6 + + r6 r4 r5 d1 d2 r3 r7 r2 c3 MX805Aj inset 1 2 xtal xtal/clock x1 r1 c1 c2 figure 2: recommended external components component notes value tolerance component notes value tolerance r1 5 1.0m 5% c3 1.5 f 20% r2 4 360k 5% c4 15.0 f, 6v tant. 20% r3 1 10.0k 5% c5 1.0 f, 10v tant. 20% r4 4 150k 5% c6 1.0 f, 10v tant. 20% r5 4 100k 5% c7 0.1 f, 25v x 7r 20% r6 150k 5% c8 1.0 f r7 6 22.0k 5% r8 2 360k 5% d1 8 c1 5 d2 8 c2 5 x1 4.00mhz table 3: recommended external components sub-audio signaling processor 8 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. recommended external component notes: 1. xtal/clock circuitry shown in inset are recommended in accordance with the mx-coms standard and dbs 800 crystal oscillators application note. 2. resistor r8 is a system component. its value is chosen together with the mx806a modulation summing amplifier to provide a subaudio signal level of C11.0db to the system modulator. 3. figure 3 and figure 4 illustrate alternative input component configurations. 4. the values for r2 and r5 are dependent on the input signal level. values given are for the specified composite signal (reference page 14). r4 add hysteresis to the comparator and is not always required. 5. the values used for c1 and c2 are determined by the frequency of x1. as a guide: 5.0mhz x1 for 18pf c2 c1 5.0mhz x1 for f p 33 2 c 1 c if the on-chip xtal oscillator is to be used, then the external components x1, c1, c2, and r1 are required as shown in figure 2 (inset). if an external clock source is used these components are not required; the input should be connected to the xtal/clock pin and the xtal pin unconnected. 6. resistor r7 is used as the dbs800 system common pull-up for the c-bus interrupt request ( irq ) line. the optimum value of this component will depend upon the circuitry connected to the irq line. 7. the level at this point should be approximately 900mv p-p. 8. silicon small signal 3.1 input configurations figure 3 shows an input configuration that is generally for use for ctcss signal and nrz data reception. input coupling capacitor c3 is required because the rx sub-audio input is held at v bias during all powered conditions of the MX805A. diodes d1 and d2 can be any silicon small signal diode. the output resistance (open loop) of the on-chip rx amp is = 6k . in the configuration shown in figure 3, the (rx amp) rc time constant is therefore 90ms. if this period is too long for some systems, i.e. those using half duplex, short data burst, and external amplifier should be considered in place of the on-chip rx amp. c4 c3 d1 r3 r5 r2 r4 d2 note 7 + + _ _ MX805A rx amp MX805A rx lpf rx sub-audio input d.c. restoration MX805A comparator comparator out comparator in rx amp in hysteresis (optional) 19 20 14 13 21 16 17 15 figure 3: MX805A input components 3.1.1 using and external op-amp for dc coupling the MX805A to the receivers discriminator output when using burst mode nrz communication, it is recommended that an additional, external op-amp is employed as configured in figure 4. this configuration will quickly compensate for sudden shift of dc input bas. components r9, r10, and r11, should be calculated to provide an accurate potential of 2.5vdc (equal to v bias ) at pin junction 15/16when using a discriminator input and 900mvp-p at the output of the external op- amp. note that the MX805A lpf has a 6db gain. if additional filtering is required, c9 should be used, it should be calculated with r9 to provide a lowpass cutoff frequency (f co ) of 500hz. sub-audio signaling processor 9 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. c9 d1 r3 100k r9 r10 v dd r11 270k d2 note 6 (see p.4) + + + _ _ _ external op-amp MX805A rx amp MX805A rx lpf gain = 6db d.c. restoration level shift and amplify MX805A comparator comparator out comparator in rx amp in from rx discriminator 19 20 14 13 21 17 16 15 15 f m figure 4: MX805A input components using and external op-amp 4 general description 4.1 glossary dcs continuous digitally coded squelch ctcss continuous tone controlled sub-audio squelch dpl tm digital private line ltr tm logic trunked radio nrz non-return-to-zero f co filter cutoff frequency f ctcss in sub-audio rx frequency f ctcss out sub-audio tx frequency f tone tone frequency f xtal xtal/clock frequency r nrzrx nrz rx baud rate r nrztx nrz tx baud rate s input audio input signal. 4.2 operating modes 4.2.1 nrz encoding the nrz encoder is formed by a shift register and the tx sub-audio lowpass filter. data loaded from the command data line is output one 8-bit byte at a time from the nrz tx data register. the output data level may be adjusted and filtered. data may be pre-emphasized via a c-bus command. the expected rx baud rate is programmed as the nrz tx baud rate (r nrztx ). see table 8 4.2.2 ctcss encoding the ctcss tone encoder is comprised of a clock divider programmed by an 11-bit binary number (q) loaded to the ctcss tx frequency register (see table 8) via the c-bus command data line. the square-wave output of the encoder is fed through the tx level adjust variable gain block to the tx sub-audio lowpass filter, a variable gain bandwidth circuit controlled by 4-bits (p) if the ctcss tx frequency register. the tx sub-audio output is a sine-wave. standard and nonstandard sub-audio tones are available. a cdcs turnoff tone may also be generated. sub-audio signaling processor 10 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 4.2.3 nrz decoding input (nrz type) sub-audio signals are filtered and the data clock extracted. decoded data is serially loaded into a shift register buffer. this data is output on 8-bit byte at a time as reply data from the nrz rx data register to the microcontroller. the expected rx baud rate is programmed as the nrz rx baud rate (r nrzrx ). see table 8. any codeword recognition can be carried out by software. 4.2.4 ctcss decoding received ctcss signals are filtered, and coherence is increased by the digital noise filter. the quality of the signal is assessed by measurement of the cycleCto-cycle period variance and, provided it is sufficiently good, the frequency is measured over a period of 122.64ms (4.0mhz crystal). if the average signal quality is consistently too low, notone is indicated; if not the input frequency is precisely indicated in the ctcss rx frequency register in a binary form. any single sub-audio tone within the specified range may be selected, enabling a dcs turnoff tone of 134hz) to be decoded while in the nrz rx mode. 5 controlling protocol control of the MX805A sub-audio signaling processors operation is by communications between the microcontroller and the MX805A internal registers on the c-bus, using address/commands (a/cs) and appended instructions or data (see figure 10). the use and content of these instructions is detailed in the following paragraphs and tables. the address select input enables the addressing of 2 separate MX805As on the c-bus to provide full-duplex signaling. 5.1 MX805A internal registers 5.1.1 control register (70 h /78 h ) write only, control and configuration of the MX805A. 5.1.2 status register (71 h /79 h ) read only, reporting of device functions. 5.1.3 ctcss rx frequency register (72 h /7a h ) read only, a 2-byte binary word indicating the frequency of the received sub-audio input. 5.1.4 ctcss tx frequency/nrz tx or rx baud rate register (73 h /7b h ) write only, a 2-byte command to set the relevant parameters. 5.1.5 nrz rx data register (74 h /7c h ) read only, a single byte f received nrz data. 5.1.6 nrz tx data register (75 h /7d h ) write only, to load a single byte of nrz data for transmission. 5.1.7 gain set register (76 h /7e h ) write only, a single byte to set the gain of the tx lowpass filter. sub-audio signaling processor 11 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 5.2 address/commands the first byte of a loaded data sequence is always recognized by the c-bus as an address/command (a/c) byte. instruction and data transactions to and from this device consist of an address/command byte followed by either: (i) further instructions or data (ii) a status or data reply instructions and data are loaded and transferred, via c-bus, in accordance with the timing information in figure 9 and figure 11. placing the address select input at a logic 0 will address MX805A #1, a logic 1 will address MX805A #2. table 4 and table 5 show the list of a/c bytes relevant to the MX805A command assignment address/command (a/c) byte data bytes hex binary msb lsb general reset 01 00000001 write to control register 70 01110000 +1 byte instruction to control register read status register 71 01110001 +1 byte reply from status register read ctcss rx freq. reg. 72 01110010 +2 byte reply of ctcss rx data write to ctcss tx freq./nrz baud rate reg. 73 01110011 +2 byte instruction for tx frequency and nrz tx/rx baud rates read nrz rx data reg. 74 01110100 +1 byte binary data reply write to nrz tx data reg. 75 01110101 +1 byte binary data command write to gain set reg. 76 01110110 +1 byte instruction for tx output table 4: MX805A #1 c-bus address/commands C (address select input at a logic 0) command assignment address/command (a/c) byte data bytes hex binary msb lsb general reset 01 00000001 write to control register 78 01111000 +1 byte instruction to control register read status register 79 01111001 +1 byte reply from status register read ctcss rx freq. reg. 7a 01111010 +2 byte reply of ctcss rx data write to ctcss tx freq./nrz baud rate reg. 7b 01111011 +2 byte instruction for tx frequency and nrz tx/rx baud rates read nrz rx data reg. 7c 01111100 +1 byte binary data reply write to nrz tx data reg. 7d 01111101 +1 byte binary data command write to gain set reg. 7e 01111110 +1 byte instruction for tx output table 5: MX805A #2 c-bus address/commands C (address select input at a logic 1) sub-audio signaling processor 12 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 5.2.1 write to control register - a/c 70h (78h) followed by 1 byte of command data table 6 shows the configurations available to the MX805A. bits 5, 6, and 7 are used together to enable and powersave circuits sections as required. setting control bits msb transmitted first 7 6 5 enabled powersaved 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ctcss decoder nrz decoder ctcss encoder nrz encoder ctcss encoder and decoder nrz encoder and ctcss decoder nrz decoder and ctcss decoder nrz decoder nrz decoder and both encoders ctcss decoder and both encoders all decoders all decoders nrz encoder and decoder no circuits all encoders all encodes except tx sub-audio lpf and ctcss decoder 4 1 0 enable audio output C used with bit 3 disable audio output C output to v bias 3 1 0 enable sub-audio bandstop filter (audio signal path) bypass sub-audio bandstop filter 2 1 0 enable all MX805A interrupts disable all MX805A interrupts 1 1 0 set rx lowpass filter bandwidth to 180hz C for low ctcss tones or nrz data set rx lowpass filter bandwidth to 260hz 0 1 0 all encoders and decoders powersaved all encoders and decoders enabled unless individually powersaved table 6: control register 5.2.2 general reset upon power-up the bits in the MX805A registers will be random (either 0 or 1). a general reset command (01 h ) will be required to reset all devices on the c-bus. it has the following effect on the MX805A: control register set to 00 h status register set to 00 h notone timer discharged warning : the following MX805A register configurations are not affected by a general rest command: ctcss rx frequency ctcss tx frequency/nrz baud rate register nrz rx data register nrz tx data register gain set register note : setting the control register in this way will set the MX805A to the ctcss decode mode and overwrite a powersave all instruction. it should also be considered that a general reset command will reset all dbs800 ics operating on the c-bus. sub-audio signaling processor 13 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 5.2.3 read status register Ca/c 71 h (79 h ) followed by 1 byte of rely data. the status register indicates the operational condition of the MX805A. bits 0 to 5 are set individually to indicate specific actions within the device. when a status bit is set to a logic 1, and interrupt request (irq) output is generated. a read of the status register will reset the interrupt and ascertain the state of this register. table 7 shows the conditions indicated by the status bits. setting set by logic cleared by logic msb received first 7, 6 not used 0 not used 0 5 nrz data transmission complete. no new data is loaded. 1 1. write to nrz data reg., or 2. general reset, or 3. nrz encoder powersave 0 4 nrz tx data buffer ready for next data byte. 1 1. write to nrz tx data reg., or 2. general rest, or 3. nrz tx powersave 0 3 new nrz rx data received before last byte was read. 1 1. read nrz rx data reg., or 2. general reset, or 3. nrz decoder powersave 0 2 1 byte of nrz data received 1 1. read nrz rx data reg., or 2. general reset, or 3. nrz decoder powersave 0 1 notone timer period expired 1 1. read status register, or 2. general rest, or 3. ctcss decoder powersave 0 0 rx tone measurement complete 1 1. read status register, or 2. general reset, or 3. ctcss decoder powersave 0 table 7: status register 5.2.4 read ctcss rx frequency register Ca/c 72 h (7a h ) followed by 2 bytes of reply data 5.2.4.1 measurement of ctcss rx frequency (f ctcss in ) the input sub-audio signal (f ctcss in ) is filtered, doubled and measured in the frequency counter over the measurement period (122.64ms) (4.0mhz xtal). the measuring function counts the number of complete input cycles occurring within the measurement period and the number of measuring-clock cycles necessary to make up one period. when the measurement period of a successful decode is complete, the rx tone measurement bit in the status register and the interrupt bit are set. the ctcss rx frequency register will now indicated the sub-audio signal frequency (f ctcss in ) in the form of 2 data bytes (1 and 0) as illustrated in figure 6. complete input cycle complete input cycle complete input cycle complete input cycle complete input cycle measuring clock cycles measurement period n r filtered and doubled sub-audio input signal 2 x f ctcss in figure 5: measurement of a ctcss rx frequency sub-audio signaling processor 14 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 5.2.4.1.1 the integer (n) Cbyte 1 the binary number representing twice the number of cmplete input sub-audio cycle periods counted during the measurement period of 122.64ms (4.0mhz crystal) 5.2.4.1.2 the remainder (r) Cbyte 0 a binary number representing the remainder part, r, of 2x the sub-audio input frequency. r = number of specified measuring-clock cycles required to complete the specified measurement period (see n). the clock cycle frequency is 4166.6hz (4.0mhz crystal) 15 14 13 12 11 10 9 8 "0" "0" integer (n) 7 6 5 43 2 1 0 "0" "0" remainder (r) byte 1 byte 0 ctcss rx frequency register (reply data) (msb) - transmitted first (reply data) (lsb) - transmitted last figure 6: format of the ctcss rx frequency register 5.2.4.2 ctcss rx frequency register the format of the ctcss rx frequency register is shown in figure 6. bits 8 (lsb) to 13 (msb) are used to represent the integer (n). from byte 1, valid values of 61 n 16 n i.e. values of n less than 16 and greater than 61 are not within the specified frequency band. bits 0 (lsb) to 5 (msb) are used to represent the remainder (r). from byte 0, valid values of 31 r . this register is not affected by the general reset command (01h) and may adopt any random configuration at power-up. 5.2.4.3 ctcss rx frequency measurement formulas to assist in the production of lookup tables and limit-values in the microcontroller, and to provide guidance upon the determination of n and r from a measured ctcss frequency, the following formulas show the derivation of the ctcss rx frequency (f ctcss in ) from the measured data bytes (n and r). 5.2.4.3.1 f ctcss in in the measurement period of 122.64ms there are n cycles at 2 x f ctcss in and r clcok cycles at 4166.6hz, for any input frequency. 5 . f x 1920 f x n - 511 int r f xf 511 x 1920 int n r) - (511 1920 f n f in ctcss xtal xtal in ctcss xtal in ctcss calculate n first example: (f xtal = 4.00mhz): f ctcss in = 100hz n = 24 r = 11; f ctcss in = 250hz n = 61 r = 3 5.2.4.4 notone timing the input sub-audio signal is monitored by the frequency assessment circuitry. before any notone action is enabled, the MX805A must have achieved at least one successful tone measurement complete action. if there is no signal or the signal is of a consistently poor quality, the notone timer will start to charge via the timing components. when the timing period has expired (at v dd /2), an interrupt and a status bit (notone timer expired) are generated. this is a one-shot function which is rest by a tone measurement complete interrupt. sub-audio signaling processor 15 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 5.2.5 write to ctcss tx frequency/nrz baud data rate register Ca/c 73 h (7b h ) followed by 2 bytes of command data. the information loaded to this register will set either the: (a) ctcss tx tone frequency f ctcss out (b) nrz tx baud rate r nrz tx (c) nrz rx baud rate r nrz rx the chosen mode for this register (a, b, or c) is determined by the MX805A modes enabled by the control register, as shown in table 8. control register bits 765 MX805A mode enabled ctcss tx/nrz baud rate register function 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ctcss decode nrz decode ctcss decode nrz encode ctcss encode and decode nrz encode & ctcss decode nrz & ctcss decode nrz decode nrz rx baud rate ctcss tx frequency nrz tx baud rate ctcss tx frequency nrz tx baud rate nrz rx baud rate nrz rx baud rate table 8 ctcss frequency/nrz baud rate register configurations 5.2.5.1 data format data is transmitted to this register as 2 bytes of command data in the form illustrated in the diagram below. this register is not affected by the general rest command (01h) and may adopt any random configuration at power-up. 15 14 13 12 11 10 9 8 "0" p 7 6 5 43 2 1 0 q byte 1 byte 0 ctcss tx frequency/nrz baud rate register (command data) (msb) - loaded first (command data) (lsb) - loaded last figure 7: format of the ctcss tx frequency/nrz baud rate register 5.2.5.2 command words p and q the two words, p and q, loaded to this register are interpreted as: p = a binary number to set the tx sub-audio lowpass filter bandwidth (applicable to nrx and ctcss modes). q = a binary number to set the frequency r baud rate of the selected functon. sub-audio signaling processor 16 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 5.2.5.2.1 command word p bits lsb 15 14 13 12 p lpf bandwidth 0 0 0 0 0 0 1 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 2 3 4 5 6 7 8 300hz 200hz 150hz 120hz 100hz 85.7hz 75hz table 9: valid values of p bits 12 to 15 are used to produce the data word p as shown in table 9. the cutoff frequency f c/o (0.5db point) of the tx sub-audio lowpass filter is calculated as: c/o xtal xtal c/o f 33 . 208 32 f p p x 208.33 x 32 f f table 9 is provided as and example and calculated using a xtal/clock (f xtal ) frequency of 4.00mhz. as illustrated, only values of p of 2 to 8 are usable 5.2.5.2.2 command word q bits 0 to 10 (see figure 7) are used to produce the data word q which sets one of the parameters described below. as you can see, command word q could be used to produce a parameter outside that specified in the characteristics section of this data bulletin. care should be taken not to do this. examples for limits of q in each operational configuration are included. q = 0 is not valid in the following calculations. bit 11 is not used and must be set to logic 0. (a) ctcss tx tone frequency (f ctcss out ) hz f x 32 f q" " so hz q" " x 32 f f out ctcss xtal xtal out ctcss f ctcss out so q f ctcss out so q = = = = 67hz 1866 250hz 500 11101001010 00111110100 (b) nrz tx baud rate (r nrz tx ) tz nrz xtal xtal tz nrz r x 32 f q" " so bits/sec q" " x 32 f r r nrz tx so q r nrz tx so q = = = = 67bits/sec 1866 300bits/sec 417 11101001010 00110100001 (c) nrz rx baud rate (r nrz rx ) rx nrz xtal xtal rx nrz r x 352 f q" " so bits/sec q" " x 11 x 32 f r r nrz rx so q r nrz rx so q = = = = 67bits/sec 114 300bits/sec 38 00001110010 00000100110 sub-audio signaling processor 17 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 5.2.6 read nrz rx data register C a/c 74 h (7c h ) followed by 1 byte reply data received nrz data bits are organized into bytes and made available to the microcontroller via the reply data line. as 8 bits are received into this register and interrupt is generated to indicate that a complete byte has been received. this byte must be read before the arrival of the last (8 th ) bit of the next incoming byte. if this in not done, an interrupt to indicate this condition will be generated and the previous rx data is discarded. see table 7. word synchronization is not provided. byte synchronization and any codeword recognition will be performed by the host microcontroller. the rx baud rate is set by writing to the ctcss tx frequency/nrz baud rate register (73 h /7b h ). the first bit received is the first bit sent to the microcontroller. this register is not affected by the general reset command (01h), and may adopt random configuration at power-up. 5.2.7 write to nrz tx data register C a/c 75 h (7d h ) followed by 1 byte of command data. a byte for transmission is loaded from the c-bus command data line with the a/c. the first data bit received via the c-bus is transmitted first. the transmitter operation is non-inverting. the first data byte loaded after the nrz encoder is enabled (control register) initiates the transmission sequence and an interrupt will be generated when the nrz tx data buffer is ready for the next data byte. subsequently, interrupts occur for every 8 bits transmitted. transmission is terminated, the tx sub-audio output is placed at v bias , and a interrupt is generated if the next byte is not loaded within 7 bit periods. see table 7. this register is not affected by the general reset command (01 h ), and may adopt any random configuration at power-up. 5.2.8 write to gain set register C a/c 76 h (7e h ) followed by 1 byte of command data 5.2.8.1 gain set register settings: the settings of this register control the ctcss and nrz signal level that is presented at the tx sub-audio output. bit 3, when enabled, is used to produce a pre-emphasis effect on the nrz tx data by increasing the gain of the data bit before a level change (see figure 8), by 1.72db to make that data pulse level slightly more positive (or negative). the signal level will be 1.72db greater that that set by bits 0 to 2. if the tx sub-audio output level is set to +2.58db, the pre-emphasis level will be +4.3db. the pre-emphasis function will remain enabled until disabled by setting bit 3 to a logic 0. if this function remains enabled when using the ctcss encoder, the output signal may be adversely affected. therefore this function should be enabled when in the nrz encode mode. this register is not affected by the general reset command (01 h ), and may adopt any random configuration at power-up. setting gain setting 7 6 5 4 transmitted bit 7 first 0 000 3 pre-emphasis setting 1 0 1.72db gain enabled 1.72db gain disabled 2 1 0 tx level adjust gain setting 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 -2.58db C1.72db C0.86db 0db +0.86db +1.72db +2.58db not used table 10: gain set register settings sub-audio signaling processor 18 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 15 14 13 12 11 10 9 8 "0" p 7 6 5 43 2 1 0 q byte 1 byte 0 ctcss tx frequency/nrz baud rate register (command data) (msb) - loaded first (command data) (lsb) - loaded last figure 8: gain set with pre-emphasisi 6 performance specifications 6.1 electrical specifications 6.1.1 absolute maximum limits exceeding these maximum ratings can result in damage to the device. general notes min. typ. max. units supply (v dd -v ss ) -0.3 7.0 v voltage on any pin to v ss -0.3 v dd + 0.3 v current v dd -30 30 ma v ss -30 30 ma any other pin -20 20 ma p / dw / lh packages total allowable power dissipation at t amb = 25 c 800 mw derating above 25 c 10 mw/ c above 25 c operating temperature -40 85 c storage temperature -55 125 c table 11: absolute maximum ratings 6.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. typ. max. units supply (v dd -v ss ) 4.5 5.0 5.5 v operating temperature -40 85 c xtal frequency 4.0 mhz table 12: operating limits sub-audio signaling processor 19 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 6.1.3 operating characteristics for the following conditions unless otherwise specified. v dd = 5.0v @ t amb = 25 c xtal/clock frequency = 4.0mhz, audio level 0db ref. = 308mv rms @ 1khz composite signal = 308mv rms @ 1khz + 75mv rms noise + 31mv rms sub-audio signal noise bandwidth = 5khz band limited gaussian notes min. typ. max. units static values supply current all functions enabled 5.0 7.0 ma all functions disabled 2.0 3.0 ma powersave all 0.9 1.5 ma analog impedances rx sub-audio input 350.0 1500.0 k audio input 350.0 k audio bypass switch on 5 2.0 k audio bypass switch off 5 1.0 6.5 m rx amp input (+ and -) 1.0 6.5 m comparator input (+ and -) 1.0 6.5 m rx sub-audio output 2.0 k tx sub-audio output encoder enabled 5 2.0 k encoder disabled 5 500.0 k audio output encoder enabled 5 2.0 k encoder disabled 5 500.0 k rx amp and comparator outputs large signal 6.0 k small signal 600.0 k dynamic values digital interface input logic 1 1 3.5 v input logic 0 1 1.5 v output logic 1 (i oh = -120ma) 2 4.6 v output logic 1 (i ol = -360ma) 3 0.4 v i out tristate (logic 1 or 0) 3 4.0 a input capacitance 1 7.5 pf logic input current (v in = 0 to 5.0v) 1 1.0 a iox (v out = 5.0v) 4 4.0 a sub-audio signaling processor 20 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. notes min. typ. max. units overall performance db ctcss - decode khz sensitivity (composite signal) 6 -20.0 -26.0 db response time (composite signal) 100hz to 257hz tone 210.0 250.0 ms 65hz tone 9 210.0 384.0 ms tone measurement resolution 0.2 % tone measurement accuracy -0.5 0.5 % notone response time (composite signal) 7 175.0 250.0 ms false tone interrupts (noise input only) 10 20.0 /hr ctcss encode frequency range 65.0 257.0 hz tone frequency resolution 0.2 % tone amplitude tolerance 12 -1.0 1.0 db rise time (to 90%) 30.0 ms fall time (to 10%) 50.0 ms total harmonic distortion 5.0 % nrx C decode rx bit rate sync time 2 edge rx bit error rate 11 1 x 10 -3 p (error) nrz C tx tx bit rate 67.0 300.0 bits/sec tx lpf (3db) bandwidth 75.0 300.0 hz sub-audio tx output level ctcss 0 db nrz 0.871 v p-p amplitude adjustment range -2.58 2.58 db adjustment step size (7 steps) 8 0.86 db sub-audio bandstop filter passband 297.0 3000.0 hz passband gain (@ 1.0khz) 0 db passband ripple (with respect to gain @ 1.0hz) -1.5 0.5 db stopband gain < 250hz 36.0 db residual hum and noise -50.0 -45.7 db alias frequency 62.5 khz receive lowpass filter (see figure 9) cutoff frequency (-3db) 280.0 hz passband gain 6.0 db xtal/clock frequency (f xtal ) 4.0 6.1 mhz table 13: operating characteristics sub-audio signaling processor 21 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. operating characteristics notes: 1. device control pins: serial clock, command data, wake , and cs . 2. reply data output 3. reply data and irq outputs 4. leakage current into the off irq output. 5. see control register 6. with input gain components set as recommended in figure 2. 7. probability 97% 8. see gain set register. 9. for f ctcss in of 65hz to 100hz, response time t r = (100/f tone ) x 250ms. 10. distributed across the rx frequency band 11. with 10db signal-to-noise ratio in a bit-rate bandwidth. 12. at any gain setting of gain register. 10db/division 0 0 800 xtal = 4.0 mhz v = 5.0v dd frequency (hz) signal level (db) 100 300 400 500 600 700 200 figure 9: typical frequency response of rx lowpass filter sub-audio signaling processor 22 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. 6.1.4 timing timing parameters for two-way communications between the c and the MX805A on the c-bus are shown in table 14. c-bus timing min. typ. max. units t cse chip select low to first serial clock rising edge 2.0 s t chs last serial clock rising edge to chip select high 4.0 s t csoff chip select high 2.0 s t nxt command data inter-byte time 4.0 s t ck serial clock period 2.0 s t ch decoder or encoder clock high 500 ns t cl decoder or encoder clock low 500 ns t cds command data set-up time 250 ns t cdh command data hold time 0 ns t rds reply data set-up time 250 ns t rdh reply data hold time 50.0 ns t hiz chip select high to reply data high C z 2.0 s table 14: timing information notes: 1. command data is transmitted to the peripheral msb (bit 7) first, lsb (bit 0) last. reply data is read from the MX805A mxb (bit 7) first, lsb (bit 0) last. 2. data is clocked into the MX805A and into the microcontroller on the rising serial clock edge. 3. loaded data instructions are acted upon at the end of each individual, loaded byte. 4. to allow for differing microcontroller serial interface formats, the MX805A will work with either polarity serial clock pulses. chip select serial clock command data reply data address/command byte first data byte last data byte first reply data byte last reply data byte logic level is not important msb lsb 76543210 76543210 76543210 msb lsb 76543210 76543210 t t t csoff t csh hiz t nxt t nxt ck t cse figure 10: c-bus timing information sub-audio signaling processor 23 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. t t t t t t t ch ck cdh rdh rds cds cl 70% vdd 30% vdd command data (from c) serial clock (from c) reply data (to c) figure 11: timing relationships for c-bus information transfer 6.2 packages note : all dimensions in inches (mm.) angles are in degrees package tolerances a b c e e1 h typ. max. min. dim. j j1 p y t k l 0.220 (5.59) 0.555 (14.04) 0.670 (17.02) 7 0.160 (4.05) 1.270 (32.26) 0.151 (3.84) 0.100 (2.54) 0.121 (3.07) 0.600 (15.24) 0.590 (14.99) 0.625 (15.88) 0.015 (0.38) 0.045 (1.14) 0.008 (0.20) 0.015 (0.38) 0.015 (0.38) 0.023 (0.58) 0.040 (1.02) 0.065 (1.65) 0.066 (1.67) 0.074 (1.88) 1.200 (30.48) 0.500 (12.70) h k l j1 j1 j j p p c c b b a a pin1 pin1 t t e e e1 e1 y figure 12: 24-pin pdip mechanical outline: order as part no. MX805Ap 0.597 (15.16) package tolerances a b c e h typ. max. min. dim. j p x w t y k l 0.105 (2.67) 0.093 (2.36) 0.419 (10.64) 45 7 0 10 0.050 (1.27) 0.046 (1.17) 0.613 (15.57) 0.299 (7.59) 0.050 (1.27) 0.016 (0.41) 0.390 (9.90) 0.020 (0.51) 0.003 (0.08) 0.009 (0.23) 0.0125 (0.32) 0.013 (0.33) 0.020 (0.51) 0.036 (0.91) 0.286 (7.26) z note : all dimensions in inches (mm.) angles are in degrees 5 5 pin 1 a b x p j y c h k e l t w z alternative pin location marking figure 13: 24-pin soic mechanical outline: order as part no. MX805Adw sub-audio signaling processor 24 MX805A 1998 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480116.004 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective compa nies. package tolerances note : all dimensions in inches (mm.) angles are in degrees a b c d e h p f g typ. max. min. dim. k j w t y 0.435 (11.05) 0.435 (11.05) 0.051 (1.30) 0.009 (0.22) 6 30 0.409 (10.40) 0.409 (10.40) 0.146 (3.70) 0.417 (10.60) 0.417 (10.60) 0.049 (1.24) 0.006 (0.152) 0.250 (6.35) 0.250 (6.35) 0.023 (0.58) 0.047 (1.19) 0.022 (0.55) 0.018 (0.45) 0.380 (9.61) 0.380 (9.61) 0.128 (3.25) 0.048 (1.22) 45 f g p a d b e pin 1 w c j k y w h t figure 14: 24-pin plcc mechanical outline: order as part no. MX805Alh |
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